1. Field Of The Invention
The invention of this application relates, in general, to digital logic circuitry and, in particular to digital flip-flop circuits.
2. Description Of The Prior Art
In digital systems it is desirable to use bi-stable memory elements which change state in response to the application of a binary input signal. This type of element is called a flip-flop. A common elementary form of the flip-flop is the "set-reset" flip-flop in which an binary input signal applied to one input called the "set" input causes the flip-flop to assume the "set" state and a corresponding binary input signal applied to the "reset" input causes the flip-flop to assume the "reset" state.
Set-reset flip-flops are useful in many of the components of digital systems. They form the basic building blocks for more complex combinatorial and sequential logic circuits such as counters, multiplexers, memories, shift registers, and others.
Prior art logic circuitry shows the set-reset flip-flop in an elementary form as a pair of coincidence gates cross-coupled so that the logic level at the output of one gate feeds back to an input of the other gate to latch the flip-flop in a stable state. Application of the appropriate input logic signal causes a change at a gate output and the cross-coupling of the output back to the input of the other gate will cause the flip-flop to assume its other stable state. Thus the flip-flop can be "set" and "reset". The elementary form of the set-reset flip-flop can consist of cross-coupled NOR gates or cross-coupled NAND gates. The choice of configuration depends upon whether logic "1" or logic "0" is the active level of the input exitation to the flip-flop.
When the basic set-reset flip-flop is used as a building block in more complex logic circuit and system applications, a variety of more complex forms emerge as is shown in the prior art. These forms include toggle flip-flops, delay flip-flops, JK flip-flops, master-slave flip-flops, and other forms, each of which have special logical characteristics.
A problem frequently encountered in the application of flip-flops in logic design is the requirement that a flip-flop memory element change state in response to a logical transition or "edge" applied to its input. This requirement can be to detect when an input signal traverses from the logic "1" state to the logic "0" state or when the input signal traverses from the logic "0" state to the logic "1" state. It is possible to solve this problem through the use of multi-level flip-flop circuit arrangements such as with two delay flip-flops or with master-slave flip-flop configurations. These solutions require large number of logic elements and, in IC applications, use up a large portion of the total area of the IC chip tending to reduce the IC fabrication yield and increase cost. Thus a simple solution to the logic design requirement of a "edge sensitive" set-reset flip-flop is highly desirable.